A backplane generally comprises a printed circuit board having a number of card connection slots or bays. Each slot or bay comprises, e.g., one or more modular signal connectors or card edge connectors, mounted on the backplane. A removable circuit board or “card” can be plugged into the connector(s) of each slot. Each removable circuit board contains drivers and receivers necessary to communicate signals across the backplane with corresponding drivers and receivers on other removable circuit boards.
One or more layers of conductive traces are formed on and/or in the backplane. The traces connect to individual signal connection points at the various slots to form data lines and control lines. Further details of the design and construction for a complex high performance router backplane are described in U.S. Pat. No. 6,822,876, issued Nov. 23, 2004, to the inventor of the present application and incorporated herein by reference.
One embodiment described in the '876 patent is reproduced in FIG. 1. A top panel region of backplane 100 has connector regions (“slots”) for sixteen cards. The outboard seven slots on each end are each configured to accept a line card (slots LC0 to LC6 and LC7 to LC13). The middlemost two slots are each configured to accept a route-processing module (slots RPM0 and RPM1). Each slot has three upper connector regions (e.g., regions JL4U0, JL4U1, and JL4U2 for slot LC4) used to distribute power and ground signals to a card. Below these, each line card slot has three high-speed connector regions (e.g., regions JLC4A, JLC4B, and JLC4C for slot LC4). The RPM slots serve more card connections than the line card slots, and therefore use a larger high-speed connector region. In one embodiment, the high-speed connector regions are laid out to accept HS3 press-fit sockets, available from Tyco Electronics Corporation (formerly AMP Incorporated).
A bottom panel region of backplane 100 contains connector regions or slots for nine cards. Each of these slots in configured to accept a switch fabric card (slots SF0 to SF8). Each slot has two lower connector regions (e.g., regions JSF8U0 and JSF8U1 for slot LC8) used to distribute power and ground signals to a switch fabric card. Above these, each switch fabric card slot has three high-speed connector regions (e.g., regions JSF8A, JSF8B, and JSF8C for slot SF8).
The bottom panel region also contains connector regions for connecting power and ground to the backplane. Four 48-volt power distribution layers are embedded in backplane 100, two for “A” power distribution and two for “B” power distribution layer. At the lower left of backplane 100, two large multi-thru-hole regions 48 VA and 48 VA RTN allow for connection of “A” power supply and return leads to one power supply, and a third large region CGND allows for connection of a common ground. Similar connections for a “B” power distribution layer to a second power supply exist at the lower right of backplane 100. The “A” and “B” power distribution systems provide redundancy for the router.
The power distribution scheme used for the backplane of FIG. 1 employs four relatively thick conductive planes near the center of the backplane for power distribution to the line and switch fabric cards. These planes provide a relatively noise-free and economic power distribution scheme for a router, as compared to more conventional power distribution approaches such as bus bars or separate power distribution circuit boards. These backplanes are believed to be the first high-speed backplanes capable of distributing 100 amperes or more of current to attached components (in this specific embodiment, two distinct power distribution planes are each capable of distributing 200 amperes of current from separate 48-volt supplies). From the 48 VA, 48 VA RTN, 48 VB, and 48 VB RTN power supply connection points shown in FIG. 1, power is fanned out to thru-holes for the switch fabric power connectors (e.g., JSF8U0 and JSF8U1) arranged along the bottom of the backplane and thru-holes for the line and RPM card power connectors (e.g., JL4U0, JL4U1, and JL4U2) arranged along the top of the backplane. This arrangement is preferred, in part, because it leaves more trace routing room near the center of the backplane for creating shorter high-speed traces. The power plane metal is removed in the high-speed connector regions, but generally covers the remainder of the backplane plan view to provide a high-current, low-resistance power path.
FIG. 2 contains a magnified view of the high-speed connector region JLC4A shown in FIG. 1, for the power plane layers L16 to L19 of backplane 100 (the layer arrangement of backplane 100 will be described further in conjunction with FIGS. 3 and 4 below). Signal throughholes are arranged in ten rows of six throughholes each, with one signal throughhole 320 identified on row eight and another signal throughhole 420 identified on row ten. A row of three digital ground throughholes is arranged between each two rows of signaling throughholes—one digital ground throughhole 310 is identified between signal rows six and seven, and another digital ground throughhole 410 is identified between signal rows nine and ten.
A minimum power clearance CP must be maintained in the backplane design, between each signal or digital ground throughhole and the power plane 210, which carries 48-volt primary power. This power clearance, including the area around the throughholes, is filled with dielectric resin 220 during the board fabrication process.
FIG. 3 illustrates the full cross-section of the material stack for backplane 100, taken through throughholes 310 and 320 as indicated in FIG. 2. The material stack of FIG. 3 has 34 conductive layers L01 to L34 and appropriate insulating layers therebetween. For each conductive layer, FIG. 3 indicates the primary purpose of that layer. Layers labeled “GND” are digital ground plane layers. Layers labeled “HSn” are the high-speed signaling layers, where n represents the layer number. These layers provide high-speed differential traces connecting various card slots. Layers labeled “Signal xn” and “Signal yn” are low-speed signaling layers, which provide other signal connections between various card slots. The two “A 48V” layers are the supply (“dc”) and return (“rtn”) for one power supply, and the two “B 48V” layers are the supply and return for the other power supply. The dotted areas between the conductive layers represent dielectric layers.
Also notable in this material stack is that each high-speed layer (with its differential signaling traces) is formed approximately equally spaced from and between two digital ground planes, e.g., high-speed layer HS1 is formed on layer L03, between ground planes at L02 and L04. Similarly, low-speed signaling layers L13 and L14 are isolated from the remaining stack by two digital grounds (L12 and L15), low-speed signaling layers L21 and L22 are isolated by two digital grounds (L20 and L23), and the four power distribution layers L15 to L19 are isolated from the remaining stack by two digital grounds (L15 and L20) at the center of the material stack. Further, the two power supply planes are placed between the two power return planes to provide yet one more layer of isolation. The result is a material stack that efficiently manages electromagnetic interference (EMI) to provide clean power distribution and good isolation for the high-speed signals.